Electrical fuse formation during a multiple patterning process
US10784195B2 · kind B2 · utility
1Cited by
4References
17Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 23, 2018 |
| Grant date | Sep 22, 2020 |
| Priority date | — |
| Expiry date | Apr 23, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5256
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.