3D NAND with integral drain-end select gate (SGD)

US10790290B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• David Daycock · Boise, US
• Purnima Narayanan · Boise, US
• John D. Hopkins · Meridian, US
• Guoxing Duan · Boise, US
• Barbara L. Casey · Meridian, US
• Christopher J. Larsen · Boise, US
• Meng-Wei Kuo · Boise, US
• Qian Tao · Singapore, SG

Key dates

• Filing date: Sep 29, 2017
• Grant date: Sep 29, 2020
• Expiry date: Nov 11, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A 3D NAND storage device includes a plurality of layers containing doped semiconductor material interleaved with a plurality of layers of dielectric material. Each of the pillars forming the 3D NAND storage device includes a plurality of memory cells and a drain-end select gate (SGD). The pillars are separated by a hollow channel in which a plurality of film layers, including at least a lower film layer and an upper film layer have been deposited. The systems and methods described herein remove at least the upper film layer proximate the SGD while maintaining the film layers proximate the memory cells. Such an arrangement beneficially permits tailoring the film layers proximate the SGD prior to depositing the channel film layer in the hollow channel. The systems and methods described herein permit the deposition of a continuous channel film layer proximate both the memory cells and the SGD.