Method for making superlattice structures with reduced defect densities
US10811498B2 · kind B2 · utility
27Cited by
71References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2018 |
| Grant date | Oct 20, 2020 |
| Priority date | — |
| Expiry date | Aug 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making a semiconductor device may include forming a superlattice on a substrate comprising a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, forming at least one of the base semiconductor portions may include overgrowing the at least one base semiconductor portion and etching back the overgrown at least one base semiconductor portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.