FinFET having upper spacers adjacent gate and source/drain contacts
US10818659B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2018 |
| Grant date | Oct 27, 2020 |
| Priority date | — |
| Expiry date | Nov 21, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Processes form integrated circuit apparatuses that include parallel fins, wherein the fins are patterned in a first direction, and parallel gate structures intersect the fins in a second direction perpendicular to the first direction. Also, source/drain structures are positioned on the fins between the gate structures, source/drain contacts are positioned on the source/drain structures, sidewall insulators are positioned between the gate structures and the source/drain contacts (wherein the sidewall insulators have a lower portion adjacent to the fins and an upper portion distal to the fins), and upper sidewall spacers are positioned between the upper portion of the sidewall insulators and the source/drain contacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.