Semiconductor apparatus having stacked gates and method of manufacture thereof

US10833078B2 · kind B2 · utility

Assignee

• TOKYO ELECTRON LIMITED · JP

Inventors

• Jeffrey Smith · Clifton Park, US
• Anton J. deVilliers · Boise, US
• Kandabara Tapily · Mechanicville, US
• Subhadeep Kal · Albany, US
• Gerrit J. Leusink · Albany, US

Key dates

• Filing date: Nov 30, 2018
• Grant date: Nov 10, 2020
• Expiry date: Nov 30, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0186
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Aspects of the disclosure provide a semiconductor apparatus that comprises a first field-effect transistor (FET) formed on a substrate and comprising a first gate, a second FET stacked on the first FET along a direction substantially perpendicular to the substrate and comprising a second gate. The semiconductor apparatus also comprises a first routing track and a second routing track electrically isolated from the first routing track. Each of the first and second routing tracks is provided on a routing plane stacked on the second FET along said direction. The semiconductor apparatus also comprises a first conductive trace configured to conductively couple the first gate of the first FET to the first routing track, and a second conductive trace configured to conductively couple the second gate of the second FET to the second routing track.