Patent · US Active

Data processing engine arrangement in a device

US10866753B2 · kind B2 · utility

15Cited by

39References

10Claims

0Family size

Assignee

XILINX, INC. · US

Inventors

Juan J. Noguera Serra · San Jose, US
Goran H K Bilski · Mölndal, SE
Jan Langer · Chemnitz, DE
Baris Ozgul · Dublin, IE
Tim Tuan · San Jose, US
Richard L. Walke · Edinburgh, GB
Ralph D. Wittig · Menlo Park, US
Kornelis A. Vissers · Sunnyvale, US
David Clarke · Dublin, IE

Key dates

Filing date	Apr 3, 2018
Grant date	Dec 15, 2020
Priority date	—
Expiry date	Aug 31, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG06F15/7807
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A device may include a plurality of data processing engines. Each of the data processing engines may include a core and a memory module. The plurality of data processing engines may be organized in a plurality of rows. Each core may be configured to communicate with other neighboring data processing engines of the plurality of data processing engines by shared access to the memory modules of the neighboring data processing engines.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.