Contact structures for integrated circuit products
US10872809B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2019 |
| Grant date | Dec 22, 2020 |
| Priority date | — |
| Expiry date | Sep 23, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76883
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One illustrative transistor device disclosed herein includes a gate structure positioned above at least an active region, wherein the gate structure has an axial length in a direction corresponding to a gate width direction of the transistor device. In this example, a first portion of the axial length of the gate structure has a first upper surface and a second portion of the axial length of the gate structure has a second upper surface, wherein the first upper surface is positioned at a level that is above a level of the second upper surface. The device also includes a gate contact structure that contacts the first upper surface of the gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.