FinFET with etch-selective spacer and self-aligned contact capping layer
US10879180B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2017 |
| Grant date | Dec 29, 2020 |
| Priority date | — |
| Expiry date | Nov 28, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In the manufacture of a FinFET device, an isolation architecture is provided between gate and source/drain contact locations. The isolation architecture may include a low-k spacer layer and a contact etch stop layer. An upper portion of the isolation architecture is removed and replaced with a high-k, etch-selective spacer layer adapted to resist degradation during an etch to open the source/drain contact locations. The high-k spacer layer, in conjunction with a self-aligned contact (SAC) capping layer disposed over the gate and overlapping a sidewall of the isolation layer, forms an improved isolation structure that inhibits short circuits or parasitic capacitance between the gate and source/drain contacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.