Patent · US Active

Through array contact structure of three- dimensional memory device

US10910397B2 · kind B2 · utility

5Cited by
9References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateDec 26, 2019
Grant dateFeb 2, 2021
Priority date
Expiry dateDec 26, 2039

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10B43/35
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The 3D NAND memory device includes an alternating layer stack disposed on a substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further comprises a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, and multiple through array contacts in the first region each extending vertically through the alternating dielectric stack. At least one through array contact is electrically connected with a peripheral circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.