Nanosheet transistors with inner airgaps
US10910470B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2019 |
| Grant date | Feb 2, 2021 |
| Priority date | — |
| Expiry date | Jul 18, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/679
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method is presented for constructing a nanosheet transistor. The method includes forming a nanosheet stack including alternating layers of a first material and a second material over a substrate, forming a dummy gate over the nanosheet stack, forming sacrificial spacers adjacent the dummy gate, and selectively etching the alternating layers of the first material to define gaps between the alternating layers of the second material. The method further includes filling the gaps with inner spacers, epitaxially growing source/drain regions adjacent the nanosheet stack, selectively removing the sacrificial spacers and the inner spacers to define cavities, and filling the cavities with a spacer material to define first airgaps adjacent the dummy gate and second airgaps adjacent the etched alternating layers of the first material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.