Transistor having double isolation with one floating isolation

US10937905B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Yongxi Zhang · Plano, US
• Philip L. Hower · Concord, US
• Sameer Pendharkar · Allen, US
• John Lin
• Guru Mathur · Plano, US
• Scott Balster · Dallas, US
• Victor Sinow · Fresno, US

Key dates

• Filing date: May 23, 2014
• Grant date: Mar 2, 2021
• Expiry date: May 14, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/516
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor device includes at least a first transistor including at least a second level metal layer (second metal layer) above a first level metal layer coupled by a source contact to a source region doped with a first dopant type. The second level metal layer is coupled by a drain contact to a drain region doped with the first dopant type. A gate stack is between the source region and drain region having the second level metal layer coupled by a contact thereto. The second level metal layer is coupled by a contact to a first isolation region doped with the second dopant type. The source region and drain region are within the first isolation region. A second isolation region doped with the first dopant type encloses the first isolation region, and is not coupled to the second level metal layer so that it electrically floats.