Encapsulated leadless package having an at least partially exposed interior sidewall of a chip carrier
US10978378B2 · kind B2 · utility
0Cited by
3References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2018 |
| Grant date | Apr 13, 2021 |
| Priority date | — |
| Expiry date | Dec 13, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A leadless package includes an at least partially electrically conductive carrier having a mounting section and a lead section, an electronic chip mounted on the mounting section, and an encapsulant at least partially encapsulating the electronic chip and partially encapsulating the carrier so that at least part of an interior sidewall of the lead section not forming part of an exterior sidewall of the package is exposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.