Transistor comprising a channel placed under shear strain and fabrication process
US10978594B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2015 |
| Grant date | Apr 13, 2021 |
| Priority date | — |
| Expiry date | Dec 22, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
Abstract
The invention relates to a field-effect transistor including an active zone including a source, a channel, a drain and a control gate, which is positioned level with said channel, allowing a current to flow through said channel between the source and drain along an x-axis, said channel including: a first edge of separation with said source; and a second edge of separation with said drain; said channel being compressively or tensilely strained, characterized in that said channel includes a localized perforation or a set of localized perforations along at least said first and/or second edge of said channel so as to also create at least one shear strain in said channel. The invention also relates to a process for fabricating said transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.