Method and apparatus for wiring multiple technology evaluation circuits
US10983159B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2018 |
| Grant date | Apr 20, 2021 |
| Priority date | — |
| Expiry date | Jul 4, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318563
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system, apparatus, and method of testing a plurality of test circuits is disclosed that includes inputting experiment data to the plurality of test circuits; applying a control signal to each of the plurality of test circuits to control application of the experiment data to the plurality of test circuits; and shifting the control signal in response to applying the control signal to each of the plurality of test circuits so that a different bit of the control signal is applied to each of the plurality of test circuits. The method in an aspect further comprises reading out a data out signal from each of the plurality of test circuits; and shifting the data out signal in response to reading out the data out signal from each of the plurality of test circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.