Multi BLCS for multi-state verify and multi-level QPW
US10984877B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2019 |
| Grant date | Apr 20, 2021 |
| Priority date | — |
| Expiry date | Dec 17, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for a multi-state verify of a memory array are provided. A sense circuit of a memory device is connected to a bit line of the memory array. The sense circuit includes a first voltage clamp, a second voltage clamp, and a program data latch disposed on the bit line. The first and second voltage clamps are biased to first and second voltages, respectively, where the first voltage is lower than the second voltage. When a high bias is applied to the program data latch, the program data latch is in an OFF state, and the first voltage clamp limits the bias on the bit line to the first voltage. When a low bias is applied to the program data latch, the program data latch is in an ON state, and the second voltage clamp limits the bias on the bit line to the second voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.