Svia using a single damascene interconnect
US11037822B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2019 |
| Grant date | Jun 15, 2021 |
| Priority date | — |
| Expiry date | May 8, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5226
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is presented for forming interlayer connections in a semiconductor device. The method includes patterning an etch stack to provide for a plurality of interlayer connections, etching guide layers following the etch stack to a first capping layer to form a plurality of guide openings, concurrently exposing a first plurality of conductive lines and a second plurality of conductive lines to form a plurality of interlayer connection openings by etching through the plurality of guide openings to remove the first capping layer, an interlayer dielectric, and a second capping layer, and depositing a metal fill in the plurality of interlayer connection openings to form the plurality of interlayer connections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.