Structure and method for equal substrate to channel height between N and P fin-FETs

US11043494B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Lawrence A. Clevenger · Saratoga Springs, US
• Leigh Anne H. Clevenger · Rhinebeck, US
• Mona A. Ebrish · Albany, US
• Gauri Karve · Cohoes, US
• Fee Li Lie · Albany, US
• Deepika Priyadarshini · Guilderland, US
• Indira Seshadri · Niskayuna, US
• Nicole Saulnier · Albany, US

Key dates

• Filing date: Jul 2, 2019
• Grant date: Jun 22, 2021
• Expiry date: Aug 28, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/85
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for fabricating fin field effect transistors comprises creating a pattern of self-aligned small cavities for P-type material growth using at least two hard mask layers, generating a pre-defined isolation area around each small cavity using a vertical spacer, selectively removing N-type material from the self-aligned small cavities, and growing P-type material in the small cavities. The P-type material may be silicon germanium (SiGe) and the N-type material may be tensile Silicon (t-Si). The pattern of self-aligned small cavities for P-type material growth is created by depositing two hard mask materials over a starting substrate wafer, selectively depositing photo resist over a plurality N-type areas, reactive ion etching to remove the second hard mask layer material over areas not covered by photo resist to create gaps in second hard mask layer, and removing the photo resist to expose the second hard mask material in the N-type areas.