Tile-based immediate mode rendering with early hierarchical-z

US11062506B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Andrew T. Lauritzen · Victoria, CA
• Altug Koker · Cameron Park, US
• Louis Feng · San Jose, US
• Tomasz Janczak · Gdańsk, PL
• David M. Cimini · Folsom, US
• Karthik Vaidyanathan · San Francisco, US
• Abhishek Venkatesh · Hillsboro, US
• Murali Ramadoss · Folsom, US
• Michael Apodaca · Folsom, US
• Prasoonkumar Surti · Folsom, US

Key dates

• Filing date: Jun 30, 2020
• Grant date: Jul 13, 2021
• Expiry date: Jun 30, 2040

Classification

• Technology area (CPC G): Physics
• CPC primary: G06T17/20
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An embodiment of a graphics pipeline apparatus may include a vertex shader, a visibility shader communicatively coupled to an output of the vertex shader to construct a hierarchical visibility structure, a tile renderer communicatively coupled to an output of the vertex shader and to the visibility shader to perform a tile-based immediate mode render on the output of the vertex shader based on the hierarchical visibility structure, and a rasterizer communicatively coupled to an output of the tile renderer to rasterize the output of the tile renderer based on the hierarchical visibility structure. Other embodiments are disclosed and claimed.