Patent · US Active

Fault-tolerant clock gating

US11099602B2 · kind B2 · utility

0Cited by

3References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Razvan Peter Figuli · Remchingen, DE
Cedric Lichtenau · Stuttgart, DE
Stefan Payer · Stuttgart, DE
Michael Klein · Schenefeld, DE

Key dates

Filing date	Apr 30, 2019
Grant date	Aug 24, 2021
Priority date	—
Expiry date	Feb 21, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH03K21/10
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A method includes obtaining a trigger signal directed to a component in a subset of components of an electronic circuit, and activating a clock corresponding with the subset of components of the electronic circuit for a preliminary period in response to the trigger signal. An active period is determined based on the trigger signal. The clock remains active for the active period. One of a timer or counter is initiated for the active period. A limit is defined for the one of the timer or counter. The active period is dynamically extended for a busy period after the one of the timer or counter is initiated. The clock is deactivated following the active period.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.