Self-aligned gate contact compatible cross couple contact formation
US11164782B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2020 |
| Grant date | Nov 2, 2021 |
| Priority date | — |
| Expiry date | Jan 8, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor device includes forming a plurality of semiconductor fins upon a substrate, forming a plurality of epitaxially grown source-drain regions upon the fins, forming a plurality of device gates upon the fins, the device gates disposed between the epitaxially grown source-drain regions, forming a trench exposing at least one epitaxially grown source-drain region, masking at least a portion of the exposed epitaxially grown source-drain region, forming a gate trench exposing at least a portion of a device gate and gate spacer, forming a metallization layer between the epitaxially grown source-drain region and the device gate, selectively recessing the metallization layer, forming a conductive layer upon the metallization layer, and forming a dielectric cap above the conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.