Three-dimensional integrated circuits (3DICs) including upper-level transistors with epitaxial source and drain material
US11164785B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2019 |
| Grant date | Nov 2, 2021 |
| Priority date | — |
| Expiry date | Jan 27, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0181
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include monocrystalline source and drain material epitaxially grown from a monocrystalline channel material at a temperature low enough to avoid degradation of a lower level transistor structure and/or degradation of one or more low-k dielectric materials between the transistor levels. A highly conductive n-type silicon source and drain material may be selectively deposited at low temperatures with a high pressure CVD process. Multiple crystals of source drain material arranged in a vertically stacked multi-channel transistor structure may be contacted by a single contact metallization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.