Artificial intelligence processor with three-dimensional stacked memory
US11171115B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2019 |
| Grant date | Nov 9, 2021 |
| Priority date | — |
| Expiry date | Mar 18, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises a ferroelectric RAM (FeRAM) having bit-cells. Each bit-cell comprises an access transistor and a capacitor including ferroelectric material. The access transistor is coupled to the ferroelectric material. The FeRAM can be FeDRAM or FeSRAM. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. The second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.