Stacked nanosheet CFET with gate all around structure
US11177258B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2020 |
| Grant date | Nov 16, 2021 |
| Priority date | — |
| Expiry date | Feb 22, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
CFET devices having a gate-all-around structure are provided. In one aspect, a method of forming a CFET device includes: forming a nanosheet device stack(s) on a substrate including alternating first/second nanosheets of a first/second material, wherein lower nanosheets in the nanosheet device stack(s) are separated from the substrate and from upper nanosheets in the nanosheet device stack(s) by sacrificial nanosheets; forming a ζ-shaped dielectric spacer separating the lower and upper nanosheets; forming lower/upper source and drains on opposite sides of the lower/upper nanosheets, separated by an isolation spacer; selectively removing the first nanosheets; and forming a first gate surrounding a portion of each of the lower nanosheets including a first workfunction-setting metal(s), and a second gate surrounding a portion of each of the upper nanosheets including a second workfunction-setting metal(s), wherein the first and second workfunction-setting metals are separated by the ζ-shaped dielectric spacer. A CFET device is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.