Three-dimensional memory devices and methods for forming the same
US11211397B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2018 |
| Grant date | Dec 28, 2021 |
| Priority date | — |
| Expiry date | Jul 27, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/80895
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a NAND memory device includes a substrate, one or more peripheral devices on the substrate, a plurality of NAND strings above the peripheral devices, a single crystalline silicon layer above and in contact with the NAND strings, and interconnect layers formed between the peripheral devices and the NAND strings. In some embodiments, the NAND memory device includes a bonding interface at which an array interconnect layer contacts a peripheral interconnect layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.