Method for fabricating an integrated circuit including a NMOS transistor and a PMOS transistor
US11217446B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2019 |
| Grant date | Jan 4, 2022 |
| Priority date | — |
| Expiry date | Apr 1, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating an integrated circuit is provided, including steps of providing a substrate including a silicon layer, a layer of insulator a layer of hard mask and accesses to first and second regions of the silicon layer; forming first and second deposits of SiGe alloy on the first and the second regions in order to form first and second stacks; then protecting the first deposit and maintaining an access to the second deposit; then performing an etch in order to form trenches between the hard mask and two opposite edges of the second stack; then forming a tensilely strained silicon layer in the second region via amorphization of the second region; then crystallization; and enriching the first region in germanium by diffusion from the first deposit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.