Contact resistance reduction in nanosheet device structure

US11289573B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Heng Wu · Guilderland, US
• Dechao Guo · Niskayuna, US
• Ruqiang Bao · Niskayuna, US
• Junli Wang · Slingerlands, US
• Lan Yu · Beijing, CN
• Reinaldo Vega · Mahopac, US
• Adra Carr · Albany, US

Key dates

• Filing date: Mar 1, 2019
• Grant date: Mar 29, 2022
• Expiry date: Mar 1, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76805
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Techniques are provided to fabricate semiconductor devices having a nanosheet field-effect transistor device disposed on a semiconductor substrate. The nanosheet field-effect transistor device includes a nanosheet stack structure including a semiconductor channel layer and a source/drain region in contact with an end portion of the semiconductor channel layer of the nanosheet stack structure. A trench formed in the source/drain region is filled with a metal-based material. The metal-based material filling the trench in the source/drain region mitigates the effect of source/drain material overfill on the contact resistance of the semiconductor device.