Memory device interface and method
US11386004B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2020 |
| Grant date | Jul 12, 2022 |
| Priority date | — |
| Expiry date | Feb 21, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some configurations, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.