Backside contacts for semiconductor devices

US11437283B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Aaron D. Lilak · Beaverton, US
• Ehren Mannebach · Beaverton, US
• Anh Phan · Beaverton, US
• Richard E. Schenker · Portland, US
• Stephanie A. Bojarski · Beaverton, US
• Willy Rachmady · Beaverton, US
• Patrick Morrow · Portland, US
• Jeffery D. Bielefeld · Forest Grove, US
• Gilbert Dewey · Beaverton, US
• Hui Jae Yoo · Hillsboro, US

Key dates

• Filing date: Mar 15, 2019
• Grant date: Sep 6, 2022
• Expiry date: Jan 3, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/85
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.