Implementing fault tolerant page stripes on low density memory systems
US11449271B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2020 |
| Grant date | Sep 20, 2022 |
| Priority date | — |
| Expiry date | Oct 23, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An example memory sub-system comprises: a memory device; and a processing device, operatively coupled with the memory device. The processing device is configured to: receive a first host data item; store the first host data item in a first page of a first logical unit of a memory device, wherein the first page is associated with a fault tolerant stripe; receive a second host data item; store the second host data item in a second page of the first logical unit of the memory device, wherein the second page is associated with the fault tolerant stripe, and wherein the second page is separated from the first page by one or more wordlines including a dummy wordline storing no host data; and store, in a third page of a second logical unit of the memory device, redundancy metadata associated with the fault tolerant stripe.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.