Patent · US Active

Three-dimensional microelectronic package with embedded cooling channels

US11462512B2 · kind B2 · utility

0Cited by
10References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateDec 28, 2020
Grant dateOct 4, 2022
Priority date
Expiry dateDec 28, 2040

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/3511
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.