Method of forming interconnect for semiconductor device
US11508617B2 · kind B2 · utility
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24References
7Claims
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Key dates
| Filing date | Oct 24, 2019 |
| Grant date | Nov 22, 2022 |
| Priority date | — |
| Expiry date | Oct 22, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53252
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an interconnect structure for semiconductor devices is described. The method comprises etching a patterned interconnect stack for form first conductive lines and expose a top surface of a first etch stop layer; etching the first etch stop layer to form second conductive lines and expose a top surface of a barrier layer; and forming a self-aligned via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.