Stacked transistors with different gate lengths in different device strata
US11573798B2 · kind B2 · utility
1Cited by
2References
23Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 1, 2019 |
| Grant date | Feb 7, 2023 |
| Priority date | — |
| Expiry date | Mar 16, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are stacked transistors with different gate lengths in different device strata, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, with two different device strata having different gate lengths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.