Selective thermal annealing method
US11581418B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2020 |
| Grant date | Feb 14, 2023 |
| Priority date | — |
| Expiry date | Jun 5, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/343
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor body having a base carrier portion and a type III-nitride semiconductor portion is provided. The type III-nitride semiconductor portion includes a heterojunction and two-dimensional charge carrier gas. One or more ohmic contacts are formed in the type III-nitride semiconductor portion, the ohmic contacts forming an ohmic connection with the two-dimensional charge carrier gas. A gate structure is configured to control a conductive state of the two-dimensional charge carrier gas. Forming the one or more ohmic contacts comprises forming a structured laser-reflective mask on the upper surface of the type III-nitride semiconductor portion, implanting dopant atoms into the upper surface of the type III-nitride semiconductor portion, and performing a laser thermal anneal that activates the implanted dopant atoms.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.