Capacitor separations in dielectric layers

US11610894B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Travis W. Lajoie · Forest Grove, US
• Abhishek A. Sharma · Hillsboro, US
• Van H. Le · Portland, US
• Chieh-Jen Ku · Hillsboro, US
• Pei-Hua Wang · Beaverton, US
• Jack T. Kavalieros · Portland, US
• Bernhard Sell · Dresden, DE
• Tahir Ghani · Portland, US
• Gregory George · Beaverton, US
• Akash Garg · Portland, US
• Julie Rollins · Forest Grove, US
• Allen B. Gardiner · Portland, US
• Shem Ogadhoh · Beaverton, US
• Juan G. Alzate Vinasco · Tigard, US
• Umut Arslan · Hillsboro, US
• Fatih Hamzaoglu · Portland, US
• Nikhil MEHTA · Portland, US
• Yu-Wen Huang · Beaverton, US
• Shu Zhou · Portland, US

Key dates

• Filing date: Jun 28, 2019
• Grant date: Mar 21, 2023
• Expiry date: Jul 18, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/30

Abstract

Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.