Vertical diode in stacked transistor architecture

US11616056B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Aaron D. Lilak · Beaverton, US
• Patrick Morrow · Portland, US
• Anh Phan · Beaverton, US
• Cheng-Ying Huang
• Rishabh Mehandru · Portland, US
• Gilbert Dewey · Beaverton, US
• Willy Rachmady · Beaverton, US

Key dates

• Filing date: Jan 18, 2018
• Grant date: Mar 28, 2023
• Expiry date: Oct 16, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/60

Abstract

An integrated circuit structure includes a first semiconductor fin extending horizontally in a length direction and including a bottom portion and a top portion above the bottom portion, a bottom transistor associated with the bottom portion of the first semiconductor fin, a top transistor above the bottom transistor and associated with the top portion of the first semiconductor fin, and a first vertical diode. The first vertical diode includes: a bottom region associated with at least the bottom portion of the first semiconductor fin, the bottom region including one of n-type and p-type dopant; a top region associated with at least the top portion of the first semiconductor fin, the top region including the other of n-type and p-type dopant; a bottom terminal electrically connected to the bottom region; and a top terminal electrically connected to the top region at the top portion of the first semiconductor fin.