Techniques for forming gate structures for transistors arranged in a stacked configuration on a single fin structure

US11616060B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Aaron D. Lilak · Beaverton, US
• Gilbert Dewey · Beaverton, US
• Willy Rachmady · Beaverton, US
• Rami Hourani · Santa Clara, US
• Stephanie A. Bojarski · Beaverton, US
• Rishabh Mehandru · Portland, US
• Anh Phan · Beaverton, US
• Ehren Mannebach · Beaverton, US

Key dates

• Filing date: Jun 29, 2018
• Grant date: Mar 28, 2023
• Expiry date: Jul 1, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0167
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

A stacked transistor architecture has a fin structure that includes lower and upper portions separated by an isolation region built into the fin structure. Upper and lower gate structures on respective upper and lower fin structure portions may be different from one another (e.g., with respect to work function metal and/or gate dielectric thickness). One example methodology includes depositing lower gate structure materials on the lower and upper channel regions, recessing those materials to re-expose the upper channel region, and then re-depositing upper gate structure materials on the upper channel region. Another example methodology includes depositing a sacrificial protective layer on the upper channel region. The lower gate structure materials are then deposited on both the exposed lower channel region and sacrificial protective layer. The lower gate structure materials and sacrificial protective layer are then recessed to re-expose upper channel region so that upper gate structure materials can be deposited.