Low latency inter-chip communication mechanism in a multi-chip processing system
US11620223B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2021 |
| Grant date | Apr 4, 2023 |
| Priority date | — |
| Expiry date | Aug 12, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/154
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.