Intermediate separation layers at the back-end-of-line

US11652047B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Travis W. Lajoie · Forest Grove, US
• Abhishek A. Sharma · Hillsboro, US
• Van H. Le · Portland, US
• Chieh-Jen Ku · Hillsboro, US
• Pei-Hua Wang · Beaverton, US
• Jack T. Kavalieros · Portland, US
• Bernhard Sell · Dresden, DE
• Tahir Ghani · Portland, US
• Gregory George · Beaverton, US
• Akash Garg · Portland, US
• Julie Rollins · Forest Grove, US
• Allen B. Gardiner · Portland, US
• Shem Ogadhoh · Beaverton, US
• Juan G. Alzate Vinasco · Tigard, US
• Umut Arslan · Hillsboro, US
• Fatih Hamzaoglu · Portland, US
• Nikhil MEHTA · Portland, US
• Ting Chen · Portland, US
• Vinaykumar Hadagali · Portland, US

Key dates

• Filing date: Jun 28, 2019
• Grant date: May 16, 2023
• Expiry date: Sep 12, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/60
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments herein describe techniques for a semiconductor device having an interconnect structure including an inter-level dielectric (ILD) layer between a first layer and a second layer of the interconnect structure. The interconnect structure further includes a separation layer within the ILD layer. The ILD layer includes a first area with a first height to extend from a first surface of the ILD layer to a second surface of the ILD layer. The ILD layer further includes a second area with a second height to extend from the first surface of the ILD layer to a surface of the separation layer, where the first height is larger than the second height. Other embodiments may be described and/or claimed.