Patent · US Active

Transistor comprising a channel placed under shear strain and fabrication process

US11688811B2 · kind B2 · utility

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4References
6Claims
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Assignee

Inventors

Key dates

Filing dateDec 16, 2020
Grant dateJun 27, 2023
Priority date
Expiry dateSep 24, 2041

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D86/60

Abstract

A field-effect transistor including an active zone comprises a source, a channel, a drain and a control gate, which is positioned level with the channel, allowing a current to flow through the channel between the source and drain along an x-axis, the channel comprising: a first edge of separation with the source; and a second edge of separation with the drain; the channel being compressively or tensilely strained, wherein the channel includes a localized perforation or a set of localized perforations along at least the first and/or second edge of the channel so as to also create at least one shear strain in the channel. A process for fabricating the transistor is provided.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.