Memory arrays and methods used in forming a memory array and conductive through-array-vias (TAVs)
US11705385B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2021 |
| Grant date | Jul 18, 2023 |
| Priority date | — |
| Expiry date | Dec 30, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/27
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method used in forming a memory array and conductive through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. A mask is formed comprising horizontally-elongated trench openings and operative TAV openings above the stack. Etching is conducted of unmasked portions of the stack through the trench and operative TAV openings in the mask to form horizontally-elongated trench openings in the stack and to form operative TAV openings in the stack. Conductive material is formed in the operative TAV openings in the stack to form individual operative TAVs in individual of the operative TAV openings in the stack. A wordline-intervening structure is formed in individual of the trench openings in the stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.