Managing error-handling flows in memory devices
US11709727B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2021 |
| Grant date | Jul 25, 2023 |
| Priority date | — |
| Expiry date | Jun 25, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a block of the memory device, wherein the block is associated with a voltage offset bin, determining an ordered set of error-handling operations to be performed to the data, determining a most recently performed error-handling operation associated with the voltage offset bin; adjusting an order of the set of error-handling operations by positioning the most recently performed error-handling operation within a predetermined position in the order of the set of error-handling operations; and performing one or more error-handling operations of the set of error-handling operations in the adjusted order until data associated to the read error is recovered.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.