Three-dimensional memory cell structure
US11723187B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2021 |
| Grant date | Aug 8, 2023 |
| Priority date | — |
| Expiry date | Jan 19, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6757
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor device, a first stack is positioned over substrate and includes a first pair of transistors and a second pair of transistors stacked over the substrate. A second stack is positioned over the substrate and adjacent to the first stack. The second stack includes a third pair of transistors and a fourth pair of transistors stacked over the substrate. A first capacitor is stacked with the first and second stacks. A second capacitor is positioned adjacent to the first capacitor and stacked with the first and second stacks. A first group of the transistors in the first and second stacks is coupled to each other to form a static random-access memory cell. A second group of the transistors in the first and second stacks is coupled to the first and second capacitors to form a first dynamic random-access memory (DRAM) cell and a second DRAM cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.