Computing system power management device, system and method
US11726543B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 3, 2020 |
| Grant date | Aug 15, 2023 |
| Priority date | — |
| Expiry date | May 5, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.