Memory device fabrication through wafer bonding

US11765908B1 · kind B1 · utility

Assignee

• Kepler Computing Inc. · US

Inventors

• Mauricio Manfrini · Dashulong, TW
• Noriyuki Sato · Hillsboro, US
• James David Clarkson · El Sobrante, US
• Abel Fernandez · Berkeley, US
• Somilkumar J. Rathi · San Jose, US
• Niloy Mukherjee · Beaverton, US
• Tanay Gosavi · Portland, US
• Amrita Mathuriya · Portland, US
• Rajeev Kumar Dokania · Beaverton, US
• Sasikanth Manipatruni · Ithaca, US

Key dates

• Filing date: Feb 10, 2023
• Grant date: Sep 19, 2023
• Expiry date: Feb 10, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B53/30

Abstract

A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.