Mitigating neighbor interference to select gates in 3D memory
US11798638B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2021 |
| Grant date | Oct 24, 2023 |
| Priority date | — |
| Expiry date | Sep 24, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technology for mitigating interference to select transistors in 3D memory is disclosed. In one aspect, a control circuit pre-charges a first set of bit lines to a first voltage and pre-charges a second set of bit lines to a second voltage greater than the first voltage. The control circuit may increase the voltage on the first set of bit lines to the second voltage while the second set of bit lines are floating to couple up the voltages on the second set of bit lines to a voltage greater than the second voltage. The higher voltage on the second set of bit lines compensates for interference that some of the select transistors may experience from an adjacent select line. For example, the higher voltage can prevent a leakage current in the select transistors from occurring. Preventing the leakage current can improve boosting of NAND channel voltages, thereby preventing program disturb.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.