Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layer
US11810784B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2021 |
| Grant date | Nov 7, 2023 |
| Priority date | — |
| Expiry date | Dec 5, 2041 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB82Y10/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making a semiconductor device may include forming a first single crystal silicon layer having a first percentage of silicon 28, and forming a superlattice above the first single crystal silicon layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The method may further include forming a second single crystal silicon layer above the superlattice having a second percentage of silicon 28 higher than the first percentage of silicon 28.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.