Multi-tier backside power delivery network for dense gate-on-gate 3D logic

US11830852B2 · kind B2 · utility

Assignee

• TOKYO ELECTRON LIMITED · JP

Inventors

• Lars Liebmann · Poughquag, US
• Jeffrey Smith · Clifton Park, US
• Daniel Chanemougame · Niskayuna, US
• Paul Gutwin · Williston, US
• Brian Tracy Cline · Austin, US
• Xiaoqing Xu · Austin, US
• David Victor Pietromonaco · San Jose, US

Key dates

• Filing date: Dec 3, 2021
• Grant date: Nov 28, 2023
• Expiry date: Jun 20, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2225/06544
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a first power delivery network (PDN) structure, and a first semiconductor device tier disposed over and electrically connected to the first PDN structure. The multi-tier semiconductor structure can further include a signal wiring tier disposed over and electrically connected to the first semiconductor device tier, a second semiconductor device tier disposed over and electrically connected to the signal wiring tier, and a second PDN structure disposed over and electrically connected to the second semiconductor device tier. The multi-tier semiconductor structure can further include a through-silicon via (TSV) structure electrically connected to the signal wiring tier, wherein the TSV structure penetrates the second PDN structure.