Semiconductor processing systems with in-situ electrical bias
US11894240B2 · kind B2 · utility
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6References
23Claims
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Key dates
| Filing date | Feb 25, 2021 |
| Grant date | Feb 6, 2024 |
| Priority date | — |
| Expiry date | Aug 30, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/67115
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system for processing semiconductor wafers, the system including: a processing chamber; a heat source; a substrate holder configured to expose a semiconductor wafer to the heat source; a first electrode configured to be detachably coupled to a first major surface of a semiconductor wafer; and a second electrode coupled to the substrate holder, the first electrode and the second electrode together configured to apply an electric field in the semiconductor wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.