Stacked trigate transistors with dielectric isolation and process for forming such

US11894372B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Willy Rachmady · Beaverton, US
• Cheng-Ying Huang
• Gilbert Dewey · Beaverton, US
• Aaron D. Lilak · Beaverton, US
• Patrick Morrow · Portland, US
• Anh Phan · Beaverton, US
• Ehren Mannebach · Beaverton, US
• Jack T. Kavalieros · Portland, US

Key dates

• Filing date: Jan 11, 2023
• Grant date: Feb 6, 2024
• Expiry date: Jan 11, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0186

Abstract

A device is disclosed. The device includes a first semiconductor fin, a first source-drain epitaxial region adjacent a first portion of the first semiconductor fin, a second source-drain epitaxial region adjacent a second portion of the first semiconductor fin, a first gate conductor above the first semiconductor fin, a gate spacer covering the sides of the gate conductor, a second semiconductor fin below the first semiconductor fin, a second gate conductor on a first side of the second semiconductor fin and a third gate conductor on a second side of the second semiconductor fin, a third source-drain epitaxial region adjacent a first portion of the second semiconductor fin, and a fourth source-drain epitaxial region adjacent a second portion of the second semiconductor fin. The device also includes a dielectric isolation structure below the first semiconductor fin and above the second semiconductor fin that separates the first semiconductor fin and the second semiconductor fin.