Contact resistance reduction in nanosheet device structure
US11894423B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2022 |
| Grant date | Feb 6, 2024 |
| Priority date | — |
| Expiry date | Feb 22, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76805
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Techniques are provided to fabricate semiconductor devices having a nanosheet field-effect transistor device disposed on a semiconductor substrate. The nanosheet field-effect transistor device includes a nanosheet stack structure including a semiconductor channel layer and a source/drain region in contact with an end portion of the semiconductor channel layer of the nanosheet stack structure. A trench formed in the source/drain region is filled with a metal-based material. The metal-based material filling the trench in the source/drain region mitigates the effect of source/drain material overfill on the contact resistance of the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.